The present invention relates to chip scale package (CSP) fabrication processes, and in particular, to CSP fabrication processes for flip chips.
In some types of semiconductor chips, the conductive pads of the chip are connected via conductive wire leads to a lead frame, and the lead frame connects the wire leads to the pins on the semiconductor package. In contrast, other types of semiconductor chips are termed flip chips. In a flip chip, conductive balls or bumps are formed on the chip, and the chip is “flipped over” in the package to connect (via a substrate or other structure) to the conductive structures of the pins. Such a flip chip does not require a lead frame or wire leads, and may therefore be made smaller than a package having a lead frame.
A typical process for fabricating a flip chip is as follows. First, semiconductor fabrication processes form the semiconductor structures on a semiconductor wafer. Second, conductive bumps or balls are formed on the top of the wafer. Third, the wafer is mounted on top of adhesive tape with the bumps on the side of the wafer opposite the tape. Fourth, the wafer is sawed into individual dies. Fifth, each individual die is flipped, mounted onto a substrate, and molded into a semiconductor package.
A number of problems arise from the above-described typical flip chip fabrication process. One such problem arises during flip chip bonding. During flip chip bonding, it is difficult to inspect the device and it is easy to cause quality issues. In addition, the bonding process is relatively high in both machine usage and raw material usage, so it is desired to develop a more efficient process.
Thus, there is a need for improved CSP fabrication processes. The present invention solves these and other problems by providing improved processes for flip chip fabrication.